24LC64T-ESLASHSN datasheet(10/24 Pages) MICROCHIP

10 / 24 page

24AA64/24LC64

DS21189F-page 10

 2002 Microchip Technology Inc.

6.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

control byte is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

6.1

Current Address Read

The 24XX64 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access was to address n (n is any legal address), the

next current address read operation would access data

from address n + 1.

Upon receipt of the control byte with R/W bit set to one,

the 24XX64 issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer but does generate a STOP condition and

the 24XX64 discontinues transmission (Figure 6-1).

6.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24XX64 as part of a write operation (R/W bit set to 0).

After the word address is sent, the master generates a

START condition following the acknowledge. This ter-

minates the write operation, but not before the internal

address pointer is set. Then the master issues the

control byte again but with the R/W bit set to a one. The

24XX64 will then issue an acknowledge and transmit

the 8-bit data word. The master will not acknowledge

the transfer but does generate a STOP condition which

causes the 24XX64 to discontinue transmission

(Figure 6-2). After a random read command, the inter-

nal address counter will point to the address location

following the one that was just read.

6.3

Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24XX64 transmits the

first data byte, the master issues an acknowledge as

opposed to the STOP condition used in a random read.

This acknowledge directs the 24XX64 to transmit the

next sequentially addressed 8-bit word (Figure 6-3).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge but will gen-

erate a STOP condition. To provide sequential reads

the 24XX64 contains an internal address pointer which

is incremented by one at the completion of each oper-

ation. This address pointer allows the entire memory

contents to be serially read during one operation. The

internal address pointer will automatically roll over from

address 1FFF to address 0000 if the master acknowl-

edges the byte received from the array address 1FFF.

FIGURE 6-1:

CURRENT ADDRESS READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA (n)

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