NE555 - SA555 - SE555

Application information

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4

Application information

4.1

Monostable operation

In the monostable mode, the timer generates a single pulse. As shown in Figure 12, the

external capacitor is initially held discharged by a transistor inside the timer.

Figure 12.

Typical schematics in monostable operation

triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered

is easily determined by Figure 14.

Note that because the charge rate and the threshold level of the comparator are both

directly proportional to supply voltage, the timing interval is independent of supply. Applying

a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2)

during the timing cycle discharges the external capacitor and causes the cycle to start over.

The timing cycle now starts on the positive edge of the reset pulse. During the time the reset

pulse is applied, the output is driven to its LOW state.

When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short-

circuit across the external capacitor and driving the output HIGH. The voltage across the

capacitor rapidly and drives the output to its LOW state.

Figure 13 shows the actual waveforms generated in this mode of operation.

When Reset is not used, it should be tied high to avoid any possibility of unwanted

triggering.

Reset

Trigger

Output

R1

C1

Control Voltage

0.01

NE555

= 5 to 15V

V

CC

4

2

3

1

5

6

7

8