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M41T00SC64 数据表(PDF) 6 Page - STMicroelectronics |
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M41T00SC64 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 19 page ![]() Pin settings M41T00SC64 6/19 2 Pin settings 2.1 Pin description 2.2 Pin connections Figure 2. 18-pin SOIC connection 1. No connect (NC) pins should be tied to VSS. 2. No function (NF) pins should be tied to VSS. Pins 2 and 3, and pins 16 and 17 are internally shorted together. 3. Open drain output. Table 1. Signal names FT/OUT (1) 1. Open drain output Frequency test / output driver (open drain) SDA Serial data address input / output SCL Serial clock WC Write control E0, E1, E2 Chip enables VBAT Battery supply voltage VCC Supply voltage VSS Ground NC (2) 2. No connect (NC) pins should be tied to VSS. No connect NF (3) 3. No function (NF) pins should be tied to VSS. Pins 2 and 3, and pins 16 and 17 are internally shorted together. No function AI09124 8 2 3 4 5 6 7 9 12 11 10 18 17 16 15 14 13 1 WC E1 NF (2) NF (2) NC (1) NF (2) NF (2) NC (1) VSS VBAT VCC E0 NC (1) E2 SDA SCL NC (1) FT/OUT (3) M41T00S + M24C64 (EEPROM) |
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