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SA1203I 数据表(PDF) 4 Page - STMicroelectronics |
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SA1203I 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 30 page  Schematic diagram TSA1203 4/30 1 Schematic diagram Figure 1. TSA1203 block diagram Figure 2. Timing diagram Timing Buffers IPOL CLK +2.5V/3.3V VINI VINBI OEB VINCMI GND VINQ VINBQ VINCMQ AD 12 I channel AD 12 Q channel 12 12 12 12 M U X REF I REF Q SELECT VREFPI VREFPQ Polar. VREFMI VREFMQ common mode common mode D0 TO D11 VCCBE GNDBE N-1 N N+1 N+6 N+7 N+2 N+5 N+3 N+4 N+8 CLK Tpd I + Tod N+9 N+10 N+11 N+12 N+13 DATA OUTPUT sample N+1 I channel sample N Q channel sample N+1 Q channel sample N+2 I channel sample N+2 Q channel sample N+3 I channel OEB Simultaneous sampling on I/Q channels SELECT sample N-9 I channel sample N-8 I channel sample N-7 Q channel sample N-6 Q channel CLOCK AND SELECT CONNECTED TOGETHER Tod I Q |
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