TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7,

Parameter

Symbol

Min.Value

Max.Value

Unit

Clock A/B "Low”

18

No Limit

ns

Clock A/B "High"

22

No Limit

ns

Clock A/B Frequency

fc

0

25

MHz

(See NOTE 1)

Clock UP/DN Reversal

100

-

ns

Delay

LCTR Positive edge to

100

-

ns

the next A/B positive or

negative edge delay

Clock A/B to

-

65

ns

CY/BW/COMP "low"

propagation delay

Clock A/B to

-

85

ns

CY/BW/COMP "high"

propagation delay

LCTR and LLTC pulse

60

-

ns

width

Clock A/B to CYT, BWT

-

100

ns

and COMPT "high"

propagation delay

Clock A/B to CYT, BWT

-

100

ns

and COMPT "low"

progagation delay

WR pulse width

60

-

ns

RD to data out delay

-

110

ns

CS, RD Terminate to

-

30

ns

Data-Bus Tri-State

Data-Bus set-up

30

-

ns

time for WR

Data-Bus hold time for WR

30

-

ns

CS set-up time for RD

0

-

ns

CS hold time for RD

0

-

ns

Back to Back RD delay

60

-

ns

RD to WR delay

-

60

-

ns

C/D set-up time for RD

0

C/D hold time for RD

30

C/D set-up time for WR

30

-

ns

C/D hold time for WR

30

-

ns

CS set-up time for WR

60

-

ns

CS hold time for WR

0

-

ns

Back to Back WR delay

Tww

60

-

ns

WR to RD delay

-

60

-

ns

Quadrature Mode:

Clock A/B Validation delay

-

160

ns

(See NOTE 1)

A and B phase delay

208

-

ns

Clock A/B frequency

-

1.2

MHz

CY, BW, COMP pulse width

85

200

ns

NOTE 1: In quadrature mode A/B inputs are filtered and required to be stable

7166-011705-6