TC510 datasheet(13/34 Pages) MICROCHIP

13 / 34 page

DS21428D-page 13

TC500/A/510/514

8.0

DESIGN CONSIDERATIONS

8.1

Noise

The threshold noise (NTH) is the algebraic sum of the

integrator and comparator noise and is typically 30

μV.

Figure 8-1 illustrates how the value of the reference

voltage can affect the final count. Such errors can be

reduced by increased integration times, in the same

way that 50/60 Hz noise is rejected. The signal-to-

noise ratio is related to the integration time (TINT) and

the integration time constant (RINT, CINT) as follows:

EQUATION 8-1:

8.2

System Timing

To obtain maximum performance from the TC5XX, the

overshoot at the end of the de-integration phase must

be minimized. Also, the integrator output zero phase

must be terminated as soon as the comparator output

returns high (see Figure 5-1).

Figure 5-1 shows the overall timing for a typical system

in which a TC5XX is interfaced to a microcontroller. The

microcontroller drives the A, B inputs with I/O lines and

monitors the comparator output (CMPTR) using an I/O

line or dedicated timer capture control pin. It may be

necessary to monitor the state of the CMPTR output in

addition to having it control a timer directly for the

Reference

de-integration

phase

(this

further

explained below.)

The timing diagram in Figure 5-1 is not to scale, as the

timing in a real system depends on many system

parameters and component value selections. There

are four critical timing events (as shown in Figure 5-1):

sampling the input polarity, capturing the de-integration

time, minimizing overshoot and properly executing the

integrator output zero phase.

8.3

Auto-zero Phase

The length of this phase is usually set to be equal to the

input signal integration time. This decision is virtually

arbitrary since the magnitudes of the various system

errors are not known. Setting the auto-zero time equal

to the Input Integrate time should be more than

adequate to null out system errors. The system may

remain in this phase indefinitely (i.e., auto-zero is the

appropriate Idle state for a TC5XX device).

8.4

Input Signal Integrate Phase

The length of this phase is constant from one

conversion to the next and depends on system

parameters and component value selections. The

calculation of TINT is shown elsewhere in this data

sheet. At some point near the end of this phase, the

microcontroller should sample CMPTR to determine

the input signal polarity. This value is, in effect, the Sign

Bit for the overall conversion result. Optimally, CMPTR

should be sampled just before this phase is terminated

by changing AB from 10 to 11. The consideration here

is that, during the initial stage of input integration when

the integrator voltage is low, the comparator may be

affected by noise and its output unreliable. Once

integration is well underway, the comparator will be in a

defined state.

8.5

Reference De-integration

The length of this phase must be precisely measured

from the transition of AB from 10 to 11 to the falling-

edge of CMPTR. The comparator delay contributes

some error in timing this phase. The typical delay is

specified to be 2

μsec. This should be considered in the

context of the length of a single count when

determining overall system performance and possible

single count errors. Additionally, overshoot will result in

charge accumulating on the integrator once its output

crosses zero. This charge must be nulled during the

integrator output zero phase.

S/N (dB)

20 log

–

-----------------------

INT

()

INT

()

•

---------------------------------------

•

⎝⎠

⎜⎟

⎛⎞

TC510 数据表(PDF) 13 Page - Microchip Technology

TC510 数据表(HTML) 13 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表下载