MCP616 datasheet(13/30 Pages) MICROCHIP

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DS21613B-page 13

MCP616/7/8/9

Now calculate the nominal DC bias point with offset:

EQUATION 4-1:

Use the worst-case specs and source values to

determine the worst-case

output voltage range and

offset for your design. Make sure the common mode

input voltage range and output voltage range are not

exceeded.

4.3

Rail-to-Rail Output

There are two specifications that describe the output

swing capability of the MCP616/7/8/9 family of op

amps. The first specification (Maximum Output Voltage

Swing) defines the absolute maximum swing that can

be achieved under the specified load conditions. For

instance, the output voltage swings to within 15 mV of

the negative rail with a 25 k

Ω load tied to VDD/2.

Figure 2-33 shows how the output voltage is limited

when the input goes beyond the linear region of

operation.

The second specification that describes the output

swing capability of these amplifiers is the Linear Output

Voltage

Range.

This

specification

defines

the

maximum output swing that can be achieved while the

amplifier still operates in its linear region. To verify

linear operation in this range, the large-signal DC

Open-Loop Gain (AOL) is measured at points inside the

supply rails. The measurement must meet the specified

AOL conditions in the specification table.

4.4

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity-gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-4) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-4:

Output Resistor, RISO

stabilizes large capacitive loads.

Figure 4-5 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN =+2V/V).

FIGURE 4-5:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Modify RISO’s value until the

response

reasonable.

Bench

evaluation

and

simulations with the MCP616/7/8/9 SPICE macro

model are helpful.

VOOS = GN [VOS + IB ((R1 ||R2 ) – REQ )

– IOS ((R1 ||R2 ) + REQ ) / 2]

VCM = VEQ – (IB + IOS /2) REQ

VOUT = VEQ (GN ) – V1 (GN – 1) + VOOS

2 R1

⁄

Where:

= op amp’s noise gain (from the

non-inverting input to the output)

VOOS = circuit’s output offset voltage

VOS

= op amp’s input offset voltage

= op amp’s input bias current

IOS

= op amp’s input offset current

VCM = op amp’s common mode input

voltage

VIN

MCP61X

RISO

VOUT

100

1,000

10,000

1.E-11

1.E-10

1.E-09

1.E-08

Normalized Load Capacitance; CL/GN (F)

10p

100

10k

100p

GN = +1

10n

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