AD9913SLASHPCBZ datasheet(25/32 Pages) AD

25 / 32 page

Data Sheet

AD9913

Rev. E | Page 25 of 32

Functionality of the I/O UPDATE and SYNC_CLK

Data from a write sequence is stored in a buffer register (data

inactive). An active register exists for every buffer register. The

I/O update signal and SYNC_CLK are used to transfer the

contents from the buffer register into the active register.

I/O_UPDATE initiates the start of a buffer transfer. It can be

sent synchronously or asynchronously relative to the SYNC_CLK.

If the setup time between the two signals is met, then constant

latency (pipeline) to the DAC output exists. For example, if

constant propagation delay of phase offset changes via the SPI

or parallel port is desired, the setup time must be met,

otherwise, a time uncertainty of one SYNC_CLK period is present.

The I/O_UPDATE is sampled by the SYNC_CLK. Therefore,

I/O_UPDATE must have a minimum pulse width greater than one

SYNC_CLK period.

The timing diagram shown in Figure 35 depicts how data in the

buffer is transferred to the active registers. An I/O_UPDATE is

not required for every register write, it can be sent after

multiple register writes.

SYNC_CLK

DATA IN

ACTIVE REGISTER

DATA IN

BUFFER REGISTER

I/O_UPDATE

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM

THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

N – 1

N + 1

N + 2

Figure 35. I/O Synchronization Timing Diagram

AD9913/PCBZ 数据表(PDF) 25 Page - Analog Devices