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AD9956/PCB 数据表(PDF) 7 Page - Analog Devices |
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AD9956/PCB 数据表(HTML) 7 Page - Analog Devices |
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7 / 32 page  AD9956 Rev. B | Page 7 of 32 Parameter Min Typ Max Unit Test Conditions/Comments Latencies/Pipeline Delays7 I/O Update to DAC Frequency Change 33 SYSCLK Cycles I/O Update to DAC Phase Change 33 SYSCLK Cycles PS<2:0> to DAC Frequency Change 29 SYSCLK Cycles PS<2:0> to DAC Phase Change 29 SYSCLK Cycles I/O Update to CP_OUT Scaler Change 4 SYSCLK Cycles I/O Update to Frequency Accumulator Step Size Change 4 SYSCLK Cycles I/O Update to Frequency Accumulator Ramp Rate Change 4 SYSCLK Cycles RF DIVIDER/CML DRIVER EQUIVALENT INTRINSIC TIME JITTER FIN = 414.72 MHz, FOUT = 51.84 MHz BW = 12 kHz −> 400 kHz 136 fS rms OC1, RF Divider R = 8 FIN = 1244.16 MHz, FOUT = 155.52 MHz BW = 12 kHz −> 1.3 MHz 101 fS rms OC3, RF Divider R = 8 FIN = 2488.32 MHz, FOUT = 622.08 MHz BW = 12 kHz −> 5 MHz 108 fS rms OC12, RF Divider R = 4 RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE FIN = 157.6 MHz, FOUT = 19.7 MHz RF Divider R = 8 @ 10 Hz −115 dBc/Hz @ 100 Hz −126 dBc/Hz @ 1 kHz −134 dBc/Hz @ 10 kHz −143 dBc/Hz @ 100 kHz −150 dBc/Hz > 1 MHz −151 dBc/Hz FIN = 1240 MHz, FOUT = 155 MHz RF Divider R = 8 @ 10 Hz −111 dBc/Hz @ 100 Hz −122 dBc/Hz @ 1 kHz −129 dBc/Hz @ 10 kHz −138 dBc/Hz @ 100 kHz −146 dBc/Hz @ 1 MHz −150 dBc/Hz >3 MHz −153 dBc/Hz FIN = 2488MHz, FOUT = 622 MHz RF Divider R = 4 @ 10 Hz −97 dBc/Hz @ 100 Hz −110 dBc/Hz @ 1 kHz −120 dBc/Hz @ 10 kHz −126 dBc/Hz @ 100 kHz −136 dBc/Hz @ 1 MHz −141 dBc/Hz >3 MHz −144 dBc/Hz TOTAL SYSTEM TIME JITTER FOR 622 MHz CLOCK See the Loop Measurement Condi- tions section 12 kHz to 5 MHz Bandwidth 0.7 ps rms |
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