MCP6021 datasheet(13/34 Pages) MICROCHIP

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DS21685C-page 13

MCP6021/1R/2/3/4

4.0

APPLICATIONS INFORMATION

The MCP6021/1R/2/3/4 family of operational amplifiers

are fabricated on Microchip’s state-of-the-art CMOS

process. They are unity-gain stable and suitable for a

wide range of general-purpose applications.

4.1

Rail-to-Rail Input

The MCP6021/1R/2/3/4 amplifier family is designed to

not exhibit phase inversion when the input pins exceed

the supply voltages. Figure 2-27 shows an input volt-

age exceeding both supplies with no resulting phase

inversion.

The input stage of the MCP6021/1R/2/3/4 family of

devices uses two differential input stages in parallel;

one operates at low common-mode input voltage

(VCM), while the other operates at high VCM. With this

topology, the device operates with VCM up to 0.3V past

either supply rail (VSS – 0.3V to VDD + 0.3V) at +25°C.

The amplifier input behaves linearly as long as VCM is

kept within the specified VCMR limits. The input offset

voltage is measured at both VCM =VSS –0.3V and

VDD + 0.3V to ensure proper operation.

Input voltages that exceed the input voltage range

(VCMR) can cause excessive current to flow in or out of

the input pins. Current beyond ±2 mA introduces

possible reliability problems. Thus, applications that

exceed this rating must externally limit the input current

with an input resistor (RIN), as shown in Figure 4-1.

FIGURE 4-1:

RIN limits the current flow

into an input pin.

Total Harmonic Distortion Plus Noise (THD+N) can be

affected by the common mode input voltage (VCM). As

shown in Figure 2-3 and Figure 2-6, the input offset

voltage (VOS) is affected by the change from the NMOS

to the PMOS input differential pairs. This change in VOS

will increase the distortion if the input voltage includes

this transition region. This transition occurs between

VDD – 1.0V and VDD – 2.0V, depending on VDD and

temperature.

4.2

Rail-to-Rail Output

The Maximum Output Voltage Swing is the maximum

swing

possible

under

particular

output

load.

According to the specification table, the output can

reach within 20 mV of either supply rail when

RL =10kΩ. See Figure 2-31 and Figure 2-34 for more

information concerning typical performance.

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases, and the closed loop bandwidth is

reduced. This produces gain-peaking in the frequency

response, with overshoot and ringing in the step

response.

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-2) improves the

feedback loop’s phase margin (stability) by making the

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

FIGURE 4-2:

Output resistor RISO

stabilizes large capacitive loads.

Figure 4-3 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-3:

Recommended RISO values

for capacitive loads.

VIN

RIN

VOUT

MCP602X

RIN ≥

(Maximum expected

VIN) - VDD

2mA

RIN ≥

VSS - (Minimum expected VIN)

2mA

VIN

MCP602X

RISO

VOUT

100

1,000

100

1,000

10,000

Normalized Capacitance; CL/GN (pF)

≥ +1

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