 2002 Microchip Technology Inc.

DS21743A-page 11

TC72

FIGURE 3-3:

Serial Interface Timing Diagrams (CP=0).

A

1

SCK

SDI

SDO

High Z

A7=1

CE

Single Byte Write Operation

(CP=0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7=1)

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

A

A

A

A

A

A

D

D

D

D

D

D

D

D

765

4

3210765

4

3210

MSb

LSb

Single Byte Read Operation

(CP=0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7=0)

CE

A

1

SCK

SDI

A7=0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

A

A

A

A

A

A

D

D

SDO

High Z

High Z

765432

1

0

MSb

LSb

70

SPI Multiple Byte Transfer

CE

SCK

Write Operation

(CP=0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7=1)

SDI

Address Byte = 80hex

High Z

SDO

Control Byte

A7

A0

D7

D0

Read Operation

(CP=0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7=0)

SDI

SDO

High Z

High Z

MSB Temp. Byte

LSB Temp. Byte

Address Byte = 02hex

Control Byte

A7

A0

D7

D0

D7

D0

D7

D0