MCP6546RT-ESLASHMS datasheet(15/32 Pages) MICROCHIP

15 / 32 page

DS21714E-page 15

MCP6546/6R/6U/7/8/9

EQUATION 4-1:

Using this simplified circuit, the trip voltage can be

calculated using the following equation:

EQUATION 4-2:

Figure 2-21 and Figure 2-24 can be used to determine

typical values for VOL. This voltage is dependent on the

output current IOL as shown in Figure 4-4. This current

can be determined using the equation below:

EQUATION 4-3:

VOH can be calculated using the equation below:

EQUATION 4-4:

As explained in Section 4.1 “Comparator Inputs”, it

is important to keep the non-inverting input below

VDD+0.3V when VPU > VDD.

4.5

Supply Bypass

With this family of comparators, the power supply pin

(VDD for single supply) should have a local bypass

capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good

edge rate performance.

4.6

Capacitive Loads

Reasonable capacitive loads (e.g., logic gates) have

little impact on propagation delay (see Figure 2-27).

The supply current increases with increasing toggle

frequency

(Figure 2-30),

especially

with

higher

capacitive loads.

4.7

Battery Life

In order to maximize battery life in portable

applications, use large resistors and small capacitive

loads. Avoid toggling the output more than necessary.

Do not use Chip Select (CS) too frequently in order to

conserve power. Capacitive loads will draw additional

power at start-up.

4.8

PCB Surface Leakage

In applications where low input bias current is critical,

PCB (Printed Circuit Board) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low-humidity conditions, a typical resistance

between nearby traces is 1012

Ω. A 5V difference

would cause 5 pA of current to flow. This is greater

than the MCP6546/6R/6U/7/8/9 family’s bias current at

25°C (1 pA, typ.).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-7.

FIGURE 4-7:

Example Guard Ring Layout

for Inverting Circuit.

Inverting Configuration (Figures 4-4 and 4-7):

Connect the guard ring to the non-inverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the

comparator (e.g., VDD/2 or ground).

Connect the inverting pin (VIN–) to the input

pad without touching the guard ring.

R23

R2R3

R2 R3

------------------

V23

R2 R3

------------------ V

VTHL

VPU

R23

R23 RF RPU

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

V23

RF RPU

R23 RF RPU

---------------------------------------

⎝⎠

⎛⎞

VTLH

VOL

R23

R23 RF

-----------------------

⎝⎠

⎜⎟

⎛⎞

V23

R23 RF

----------------------

⎝⎠

⎛⎞

VTLH = trip voltage from low to high

VTHL = trip voltage from high to low

IOL

IPU IRF

IOL

VPU VOL

–

RPU

--------------------------

⎝⎠

⎛⎞

V23 VOL

–

R23 RF

------------------------

⎝⎠

⎛⎞

VOH

VPU V23

–

()

R23 RF

R23 RF RPU

--------------------------------------

⎝⎠

⎛⎞

Guard Ring

VIN-VIN+

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