MCP1256 datasheet(13/24 Pages) MICROCHIP

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DS21989A-page 13

MCP1256/7/8/9

4.6

Power-Good Output (PGOOD)

For the MCP1256/8 devices, the PGOOD output is an

open-drain output that sinks current when the regulator

output voltage falls below 0.93VOUT (typical). If the reg-

ulator output voltage falls below 0.93VOUT (typical) for

less than 200 μs and then recovers, glitch immunity cir-

cuits prevent the PGOOD signal from transitioning low.

A 10 k

Ω to 1 MΩ pull-up resistor from PGOOD to VOUT

may be used to provide a logic output. If not used,

connect PGOOD to GND or leave unconnected.

PGOOD is high impedance when the output voltage is

in regulation. A logic low is asserted when the output

falls 7% (typical) below the nominal value. The PGOOD

output remains low until VOUT is within 3% (typical) of

its nominal value. On start-up, this pin indicates when

the output voltage reaches its final value. PGOOD is

high impedance when SHDN is low or when BYPASS

is low (MCP1258).

4.7

Low-Battery Output (LBO)

For the MCP1257/9 devices, the LBO output is an

open-drain output that sinks current when the input

voltage falls below a preset threshold. If the input volt-

age falls below the preset threshold for less than

200 μs and then recovers, glitch immunity circuits pre-

vent the LBO signal from transitioning low. A 10 k

Ω to

Ω pull-up resistor from LBO to VOUT may be used

to provide a logic output. If not used, connect LBO to

GND or leave unconnected.

LBO is high impedance when the input voltage is above

the low-battery threshold voltage. A logic low is

asserted when the input falls below the low-battery

threshold voltage. The LBO output remains low until

VIN is above the low-battery threshold voltage plus the

low-battery hysteresis voltage. LBO is high impedance

when SHDN is low or when BYPASS is low

(MCP1259).

4.8

Soft-Start and Short-Circuit

Protection

The MCP1256/7/8/9 devices feature fold back short-

circuit protection. This circuitry provides an internal

soft-start function by limiting inrush current during

startup and also limits the output current to 150 mA

(typical), if the output is short-circuited to GND. The

internal soft-start circuitry requires approximately

175 μs, typical, from either initial power-up, release

from Shutdown, or release from BYPASS (MCP1258/9)

for the output voltage to be in regulation.

4.9

Thermal Shutdown

The MCP1256/7/8/9 devices feature thermal shutdown

with temperature hysteresis. When the die temperature

exceeds 160°C, the device shuts down. When the die

cools by 15°C, the MCP1256/7/8/9 automatically turns

back on again. If high die temperature is caused by out-

put overload and the load is not removed, the device

will turn on and off resulting in a pulsed output.

5.0

APPLICATIONS

5.1

Capacitor Selection

The style and value of capacitors used with the

MCP1256/7/8/9 family determine several important

parameters, such as output voltage ripple and charge

pump strength. To minimize noise and ripple, it is rec-

ommended that low ESR (0.1

Ω) capacitors be used for

both CIN and COUT. These capacitors should be

ceramic and should be 10 μF or higher for optimum

performance.

If the source impedance to VIN is very low, up to several

megahertz, CIN may not be required. Alternatively, a

somewhat smaller value of CIN may be substituted for

the recommended 10 μF, but will not be as effective in

preventing ripple on the VIN pin.

The value of COUT controls the amount of output volt-

age ripple present on VOUT. Increasing the size of

COUT will reduce output ripple at the expense of a

slower turn-on time from shutdown and a higher inrush

current.

The flying capacitors (C1 and C2) control the strength

of the charge pump and in order to achieve the maxi-

mum rated output current (100 mA), it is necessary to

have at least 1 μF of capacitance for the flying capaci-

tor. A smaller flying capacitor delivers less charge per

clock cycle to the output capacitor resulting in lower

available output current.

5.2

PCB Layout Issues

The MCP1256/7/8/9 devices transfer charge at high

switching frequencies producing fast, high peak, tran-

sient currents. As a result, any stray inductance in the

component layout will produce unwanted noise in the

system. Proper board layout techniques are required to

ensure optimum performance.

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