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MCP3551-E/MS 数据表(PDF) 21 Page - Microchip Technology

部件名 MCP3551-E/MS
功能描述  Low-Power, Single-Channel 22-Bit Delta-Sigma ADCs
PDF  30 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP3551-E/MS 数据表(HTML) 21 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
DS21950D-page 21
MCP3550/1/3
5.5
Using The MCP3550/1/3 with
Microcontroller (MCU) SPI Ports
It is required that the microcontroller SPI port be config-
ured to clock out data on the falling edge of clock and
latch data in on the rising edge. Figure 5-6 depicts the
operation shown in SPI mode 1,1, which requires that
the SCK from the MCU idles in the High state, while
Figure 5-7 shows the similar case of SPI Mode 0,0,
where the clock idles in the Low state. The waveforms
in the figures are examples of an MCU operating the
SPI port in 8-bit mode, and the MCP3550/1/3 devices
do not require data in 8-bit groups.
In SPI mode 1,1, data is read using only 24 clocks or
three byte transfers. The data ready bit must be read
by testing the SDO/RDY line prior to a falling edge of
the clock.
In SPI mode 0,0, data is read using 25 clocks or four
byte transfers. Please note that the data ready bit is
included in the transfer as the first bit in this mode.
FIGURE 5-6:
SPI Communication – Mode 1,1.
FIGURE 5-7:
SPI Communication – Mode 0,0.
CS
SCK
SDO/RDY
MCU
Data stored into MCU receive
register after transmission of
first byte
Receive
Buffer
Data stored into MCU receive
register after transmission of
second byte
Data stored into MCU receive
register after transmission of
third byte
DO O
21 20 19 18 17
16
15 14 13 12 11 10 9
8
7 6 543
2 1
0
OL OH 21 20 19 18 17 16
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RH L
CS
SCK
SDO/RDY
MCU
Data stored into MCU receive
register after transmission of
first byte
Receive
Buffer
Data stored into MCU receive
register after transmission of
second byte
Data stored into MCU receive
register after transmission of
third byte
Data stored into MCU receive
register after transmission of
fourth byte
DR
OO
21 20 19 18 17
16
14 13 12 11 10 9
654 3 2
0
OH OL 21 20 19 18 17
15 14 13 12 11 10 9
7
6
5
4
3
2
1
0
DR
8
16
15
7
8
1
HL



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