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MCP6G01RT-E/SL 数据表(PDF) 9 Page - Microchip Technology |
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MCP6G01RT-E/SL 数据表(HTML) 9 Page - Microchip Technology |
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9 / 38 page ![]() © 2006 Microchip Technology Inc. DS22004B-page 9 MCP6G01/1R/1U/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: Unless otherwise indicated, TA =+25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G, RL =100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low. FIGURE 2-1: DC Gain Error, G = +1. FIGURE 2-2: DC Gain Error, G ≥ +10. FIGURE 2-3: Input Offset Voltage. FIGURE 2-4: DC Gain Drift, G = +1. FIGURE 2-5: DC Gain Drift, G ≥ +10. FIGURE 2-6: Input Offset Voltage Drift. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 5% 10% 15% 20% 25% 30% DC Gain Error (%) 2460 Samples G = +1 0% 2% 4% 6% 8% 10% 12% 14% DC Gain Error (%) 4916 Samples G ≥ +10 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% Input Offset Voltage (mV) 2460 Samples G = +50 G = +10 G = +1 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% DC Gain Drift (ppm/°C) 2459 Samples G = +1 TA = -40 to +125°C 0% 2% 4% 6% 8% 10% 12% 14% DC Gain Drift (ppm/°C) 4912 Samples G ≥ +10 TA = -40 to +125°C 0% 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 22% Input Offset Voltage Drift (µV/°C) 1612 Samples G = +1, +10, +50 TA = -40 to +125°C |
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