24LC512-ISLASHMS datasheet(19/42 Pages) MICROCHIP

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DS21930B-page 19

24AAXX/24LCXX/24FCXX

8.0

READ OPERATION

Read operations are initiated in much the same way as

write operations with the exception that the R/W bit of

the control byte is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 24XX contains an address counter that maintains

the address of the last byte accessed, internally incre-

mented by ‘1’. Therefore, if the previous read or write

operation was to address ‘

n’ (n is any legal address),

the next current address read operation would access

data from address

n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24XX issues an acknowledge and transmits the

8-bit data byte. The master will not acknowledge the

transfer, but does generate a Stop condition and the

24XX discontinues transmission (Figure 8-1).

FIGURE 8-1:

CURRENT ADDRESS

READ

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the byte address must first

be set. This is done by sending the byte address to the

24XX as part of a write operation (R/W bit set to ‘0

’).

Once the byte address is sent, the master generates a

Start condition following the acknowledge. This termi-

nates the write operation, but not before the internal

address counter is set. The master then issues the

control byte again, but with the R/W bit set to a ‘1’. The

24XX will then issue an acknowledge and transmit the

8-bit data byte. The master will not acknowledge the

transfer but does generate a Stop condition, which

causes the 24XX to discontinue transmission

(Figure 8-2 and Figure 8-3). After a random Read

command, the internal address counter will increment

to the next address location.

FIGURE 8-2:

RANDOM READ: 128-BIT TO 16 KBIT DEVICES

FIGURE 8-3:

RANDOM READ: 32 TO 512 KBIT DEVICES

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data

Byte

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Address

Byte (n)

Control

Byte

Data

Byte

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

High Order

Address Byte

Low Order

Address Byte

Control

Byte

Data

Byte

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