AD823A

Data Sheet

Rev. | Page 14 of 20

THEORY OF OPERATION

The AD823A is a dual voltage feedback amplifier with an

N-channel JFET input stage and a rail-to-rail bipolar output

stage. It is fabricated on the Analog Devices, Inc. XFCB process,

a dielectrically isolated complementary bipolar process featuring

high speed 36 V bipolar devices along with JFETs and thin film

resistors. The N-channel input stage handles signals up to 200 mV

below the negative supply while maintaining picoamp level

input currents. The rail-to-rail output maximizes the amplifier’s

output range and can provide up to 40 mA linear drive current

with output voltages within .5 V of either power rail. Laser-

trimmed thin film resistors are used to optimize offset voltage

(3.5 mV max over the entire supply range) and offset voltage

drift (typical 1 uV/°C).

Figure 38 shows the architecture of an amplifier. Two stages are

used, with the first stage folded cascode input driving the

differential input of the second stage output. The voltage swing

at nodes S1p and S1n are kept small to minimize the generation

of nonlinear currents due to junction capacitances. This improves

distortion performance. Inputs and outputs of the amplifier are

fully protected with dedicated ESD diodes.

OUTPUT IMPEDANCE

The low frequency open-loop output impedance of the common-

emitter output stage used in this design is approximately 50 kΩ.

Although this is significantly higher than a typical emitter follower

output stage, when it is connected with feedback, the open-loop

gain of the op amp reduces the output impedance.

With 105 dB of open-loop gain, the output impedance is reduced

to <0.01 Ω. At higher frequencies, the output impedance rises as

the open-loop gain of the op amp drops; however, the output also

becomes capacitive due to the integrator capacitor. This

prevents the output impedance from ever becoming excessively

high (see Figure 21), which can cause stability problems when

driving capacitive loads. In fact, the AD823A has excellent

capacitive load drive capability for a high frequency op amp.

Figure 36 shows the results of the AD823A connected as a

follower while driving a 470 pF direct capacitive load. Under

these conditions, the phase margin is approximately 35°. For a

greater phase margin, use a low value resistor in series with the

output to decouple the effect of the load capacitance from the

op amp (see Figure 28). In addition, running the part at higher

gains also improves the capacitive load drive capability of the

op amp.

+VS

–IN

+IN

OUT

–VS

VBIAS

S1P

S1N

OUTPUT

DRIVE

Figure 38. Simplified Schematic

B