Data Sheet

AD8027/AD8028

THEORY OF OPERATION

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Rev. E | 20 of 27

The AD8027/AD8028 are rail-to-rail input/output amplifiers de-

signed in the Analog Devices, Inc., extra fast complementary

bipolar (XFCB) process. The XFCB process enables the AD8027/

AD8028 to run on 2.7 V to 12 V supplies with 190 MHz of band-

width and a 100 V/µs slew rate. The AD8027/AD8028 have 4.3

nV/√Hz of wideband noise with 17 nV/√Hz noise at 10 Hz. This

noise performance, with an offset of less than 900 µV maximum

and drift performance of 1.50 µV/°C typical, makes the AD8027/

AD8028 ideal for high speed, precision applications. Additionally,

the input stage operates 200 mV beyond the supply rails and shows

no phase reversal. The amplifiers feature overvoltage protection on

the input stage. When the inputs exceed the supply rails by 0.7 V,

ESD protection diodes turn on, drawing excessive current through

the differential input pins. Include a series input resistor to limit the

input current to less than 10 mA.

INPUT STAGE

The rail-to-rail input performance is achieved by operating comple-

mentary input pairs. The common-mode level of the differential

input signal determines which pair is on. As shown in Figure 60,

a tail current (ITAIL) is generated that sources the PNP differential

input structure consisting of Q1 and Q2. A reference voltage is

generated internally that is connected to the base of Q5. This

voltage is continually compared against the common-mode input

voltage. When the common-mode level exceeds the internal refer-

ence voltage, Q5 diverts the tail current (ITAIL) from the PNP input

pair to a current mirror that sources the NPN input pair consisting of

Q3 and Q4.

The NPN input pair can then operate at 200 mV above the positive

rail. Both input pairs are protected from differential input signals

above 1.4 V by four diodes across the input (see Figure 60). In

the event of differential input signals that exceed 1.4 V, the diodes

conduct and excessive current flows through them. Include a series

input resistor to limit the input current to 10 mA.

CROSSOVER SELECTION

The AD8027/AD8028 have a crossover selection feature that allows

the user to choose the crossover point between the PNP/NPN

differential pairs. Although the crossover region is small, avoid oper-

ating in this region because it can introduce offset and distortion to

the output signal. To help avoid operating in the crossover region,

the AD8027/AD8028 allow the user to select from two preset

crossover locations (voltage levels) using the DISABLE/SELECT

pin. The crossover region is about 200 mV and is defined by the

voltage level at the base of Q5 in Figure 60. Internally, two separate

voltage sources are created approximately 1.2 V from either rail.

One rail or the other is connected to Q5, based on the voltage

applied to the DISABLE/ SELECT pin. This allows either dominant

PNP pair operation, when the DISABLE/SELECT pin is left open,

or dominant NPN pair operation, when the DISABLE/SELECT pin is

pulled high.

The DISABLE/SELECT pin also provides the traditional power-

down function when it is pulled low. This pin allows the designer

to achieve the best precision and ac performance for high-side and

low-side signal applications. See Figure 54 through Figure 57 for

DISABLE/SELECT pin characteristics.

In the event that the crossover region cannot be avoided, specific

attention is given to the input stage to ensure constant transconduc-

tance and minimal offset in all regions of operation. The regions are

PNP input pair running, NPN input pair running, and both running at

the same time (in the 200 mV crossover region). Maintaining con-

stant transconductance in all regions ensures the best wideband

distortion performance when going between these regions. With

this technique, the AD8027/AD8028 can typically achieve 85 dBc

SFDR for a 2 V p-p, 1 MHz, and G = +1 signal on ±1.5 V supplies.

Another requirement needed to achieve this level of distortion is

that the offset of each pair must be laser trimmed, even for low

frequency signals.

Figure 60. Simplified Input Stage