TDA8752 datasheet(19/36 Pages) PHILIPS

19 / 36 page

1999 Mar 09

Philips Semiconductors

Product speciﬁcation

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

Table 5

Charge-pump current control

The default programmed value is as follows:

• Charge pump current = 100 µA

• Test bits: no test mode; bits Up and Do at logic 0

• Rising edge of CKREF: bit edge at logic 0

• COAST and HSYNC inputs are active HIGH: V level and

H level at logic 0.

VCO REGISTER

The bits Z2, Z1 and Z0 enable the internal resistance for

the VCO filter to be selected.

Table 6

VCO register bits

Ip2

Ip1

Ip0

CURRENT

(

µA)

6.25

12.5

010

011

100

101

200

110

400

111

700

RESISTANCE

Ω)

high impedance

001

128

010

011

100

101

110

111

Table 7

VCO gain control

The bits VCO1 and VCO0 control the VCO gain.

The default programmed value is as follows:

• Internal resistance = 16 kΩ

• VCO gain = 15 MHz/V.

DIVIDER REGISTER

This register controls the PLL frequency. The bits are the

LSB bits.

The default programmed value is 0011 0010 0000 = 800.

The MSB bits (Di11, Di10, Di9) and the LSB bit (Di0) have

to be programmed before the bits Di8 to Di1 to have the

required divider ratio. The bit Di0 is used for the parity

divider number = Di0 = 0 = even number Di0 = 1 = odd

number. It should be noted that if the I2C-bus programming

is done in mode = 1 and the bit Di0 has to be toggled, then

the registers have to be loaded twice to have the update

divider ratio.

POWER-DOWN MODE

• When the supply is completely switched off, the

registers are set to their default values; in that event they

have to be reprogrammed if the required settings are

different (e.g. through an EEPROM)

• When the device is in power-down mode, the previously

programmed register values remain unaffected.

PHASEA AND PHASEB REGISTERS

The bit Cka is logic 0 when the used clock is the PLL clock,

and logic 1 when the used clock is the external clock.

The bit Ckb is logic 0 when the second clock is not used.

The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program

the phase shift for the clock, CKADCO, CKAO and CKBO

(see Table 8).

VCO1

VCO0

VCO gain

(MHz/V)

PIXEL CLOCK

FREQUENCY

RANGE (MHz)

10 to 17

17 to 35

35 to 60

100

60 to 100

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