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93LC46AT-E/MS 数据表(PDF) 8 Page - Microchip Technology

部件名 93LC46AT-E/MS
功能描述  1K Microwire Compatible Serial EEPROM
PDF  28 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

93LC46AT-E/MS 数据表(HTML) 8 Page - Microchip Technology

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93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
DS21749F-page 8
© 2005 Microchip Technology Inc.
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
VCC must be
≥ 4.5V for proper operation of ERAL.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
TCSL
Check Status
10
0
1
0
x
•••
x
TSV
TCZ
Busy
Ready
High-Z
TEC
High-Z
VCC must be
≥ 4.5V for proper operation of ERAL.
CS
CLK
DI
DO
TCSL
Check Status
10
0
1
0
x
•••
x
TSV
TCZ
Busy
Ready
High-Z
TEC
High-Z



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