Data Sheet

AD8244

INPUT PROTECTION

All terminals of the AD8244 are protected against ESD. In

addition, the input structure allows for dc overload conditions

up to a diode drop above the positive supply and a diode drop

below the negative supply. Voltages more than a diode drop beyond

the supplies cause the ESD diodes to conduct and enable current

to flow through the diode. Therefore, use an external resistor in

series with each of the inputs to limit current for voltages beyond

the supplies. In either scenario, the AD8244 input safely handles

a continuous 6 mA current at room temperature.

For applications where the AD8244 encounters extreme overload

voltages, as in cardiac defibrillators, use external series resistors

and low leakage diode clamps, such as FJH1100 or BAV199L.

LAYOUT CONSIDERATIONS

The inputs of the AD8244 buffers are extremely high impedance.

Shunt impedances from leakage resistance and parasitic

capacitance in the printed circuit board (PCB) layout can severely

degrade the performance of the JFET input. If a buffer output is

used to surround the corresponding input node, leakage

resistance and parasitic capacitance from the layout can be kept

extremely low. Remove solder mask from the guard traces to

guard against surface leakage due to contamination. In addition to

the guard traces on the primary side, route a guard trace around

any vias in the input net on the other side of the board as well.

Keep the parasitic capacitance seen by the output small to

maintain the optimum step response. Amplifiers used in the same

signal path, such as buffering the voltage for two inputs of an in-

amp or difference amplifier, must have matched impedance in

the input traces. This includes matched length and symmetrical

traces. Place any input resistors close to the AD8244 inputs to

avoid interaction with trace parasitics. If one of the channels is

not in use, connect the input to a voltage that is within its linear

range to avoid overdrive conditions that can interfere with other

channels. Leave the output unconnected. Place decoupling

capacitors, such as 0.1 µF, near the AD8244. Larger capacitors,

such as 10 µF, can be used farther away from the device.

DIFFERENTIAL SIGNAL CHAINS

The AD8244 can be used to buffer the inputs of difference

amplifiers and instrumentation amplifiers to take advantage of

qualities of the JFET input. In applications such as these, which

use two channels of the AD8244 to buffer the positive and negative

of a differential signal path, it is the mismatch between the

channels, rather than the absolute error, that introduces error

into the system. The AD8244 is designed so that the channels

closely match and can be used in differential circuits with

excellent results. Channel-to-channel matching errors are

specified to aid in the design process. When driving the inputs

of an instrumentation amplifier, difference amplifier, or other

differential input circuit, the gain matching from channel to

channel defines the common-mode rejection ratio (CMRR)

error introduced to the system by the AD8244. The unit

conversion is as follows:

CMRR (dB) = 20 × log10(100/Gain Matching (%))

The JFET pinch-off voltage can vary from channel to channel

and cause additional mismatch when the JFET begins to saturate

near the positive rail. The CMRR error is minimized by keeping

the input voltage away from the positive input range limit. Because

the input impedance is very high, the CMRR achieved in

differential systems stays high, even with large or mismatched

source resistance. See the Typical Performance Characteristics

section for more information.

LOW OUTPUT IMPEDANCE vs. FREQUENCY

The closed-loop output impedance of the AD8244 increases at

higher frequencies when the loop gain is reduced, as shown in

Figure 12. The AD8244 drives 200 pF directly with slight

ringing, as shown in Figure 35. By placing a small resistor in

series with the output, the capacitive load drive of the AD8244

can be increased. For applications that need the AD8244 input

performance and very low output impedance over frequency,

such as driving a cable shield, a switching load, or a large

amount of capacitance at high frequencies, an op amp can be

added in a configuration, such as the one in Figure 41. This

configuration takes advantage of the low op amp output

impedance at low frequencies, and the load capacitor reduces

the output impedance at high frequencies. Typically, RF × CF

should be less than or equal to RO × CL.

1/4

AD8244

A1

VOUT

CF

RF

VIN

RO

CL

RS

Figure 41. Adding an Op Amp for Low Output Impedance

Rev. A | Page 15 of 20