DS2406

TWO-CHANNEL WRITE Figure 10c

1-WIRE

td1

PIO-A

15 µs < td1 < 60 µs

200 ns < td0 < 300 ns

PIO-B

PIO-A

PIO-B

IC=1, SYNCHRONOUS MODE

IC=0, ASYNCHRONOUS MODE

A1

B1

A2

B2

A3

B3

A4

B4

A1

A2

A3

A4

B1

B2

B3

B4

A1

A2

A3

A4

B1

B2

B3

B4

td0

1-WIRE BUS SYSTEM

The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances, the

DS2406 is a slave device. The bus master is typically a microcontroller. The discussion of this bus

system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire

signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state

during specified time slots that are initiated on the falling edge of sync pulses from the bus master.

HARDWARE CONFIGURATION

The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to

drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an

open drain or 3-state outputs. The 1-Wire port of the DS2406 is open drain with an internal circuit

equivalent to that shown in Figure 11. Typical bus master ports are shown in Figure 12. If a bi-directional

pin is not available, separate output and input pins can be tied together. A multidrop bus consists of a 1-

Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3kbits/s. For

normal communication excluding EPROM programming the 1-Wire bus requires only a pull-up resistor

of approximately 5k

Ω for short line lengths.

The idle state for the 1-Wire bus is high. If, for any reason a transaction needs to be suspended, the bus

MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low

for more than 120µs, one or more of the devices on the bus may be reset. If the 1-Wire bus remains low

both PIOs.

TRANSACTION SEQUENCE

The sequence for accessing the DS2406 via the 1-Wire port is as follows:

Initialization

ROM Function Command

Memory or Channel Access Function Command

Transaction/Data

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