Data Sheet

AD708

Rev. D | Page 11 of 16

OPERATION WITH A GAIN OF −100

To show the outstanding dc precision of the AD708 in a real

application, Table 3 shows an error budget calculation for a gain

of −100. This configuration is shown in Figure 28.

Table 3.

Error Sources

Maximum Error Contribution, AV = 100

(S Grade), (Full Scale: VOUT = 10 V, VIN = 100 mV)

VOS

30 μV/100 mV

= 300 ppm

IOS

(100 kΩ)(1 nA)/10 V

= 10 ppm

Gain (2 kΩ Load)

10 V/(5 × 106)/100 mV

= 20 ppm

Noise

0.35 mV/100 mV

= 4 ppm

VOS Drift

(0.3 mV/°C)/100 mV

= 3 ppm/°C

Total Unadjusted

Error

At 25°C

= 334 ppm > 11 bits

−55°C to +125°C

= 634 ppm > 10 bits

With Offset

Calibrated Out

At 25°C

= 34 ppm > 14 bits

−55°C to +125°C

= 334 ppm > 11 bits

1/2

AD708

VOUT

VIN

+

–

100kΩ

1kΩ

1kΩ

2

3

8

4

1

0.1µF

0.1µF

+VS

–VS

Figure 28. Gain of −100 Configuration

This error budget assumes no error in the resistor ratio and no

error from power supply variation (the 120 dB minimum PSRR

of the AD708S makes this a good assumption). The external

resistors can cause gain error from mismatch and drift over

temperature.

HIGH PRECISION PROGRAMMABLE GAIN

AMPLIFIER

The 3-op-amp programmable gain amplifier shown in Figure 29

utilizes the matching characteristics of the AD708 to achieve

high dc precision.

S3B

VDD

VSS

S1A

S2A

A0

A1

S3A

S4A

S4B

S2B

S1B

ADG1209

DA

DB

1/2

AD708

VINA

1/2

AD708

VINB

10kΩ

10kΩ

10kΩ

10kΩ

1kΩ

10kΩ

10kΩ

100Ω

10kΩ

AD8276

REF

SENSE

VOUT

Figure 29. Precision PGA

The gains of the circuit are controlled by the select lines, A0 and

A1, of the ADG1209 multiplexer and are 1, 10, 100, and 1000 in

this design.

The input stage attains very high dc precision due to the 30 μV

maximum offset voltage match of the AD708 and the 1 nA

maximum input bias current match. The accuracy is main-

tained over temperature because of the ultralow drift

performance of the AD708.

The AD8276 unity-gain difference amplifier eliminates the need

for trimming in the second stage of the instrumentation

amplifier. The AD8276 has on-chip resistors that are laser

trimmed for excellent gain accuracy and high CMRR.

To determine the CMRR, follow these steps:

1.

Connect VINB to VINA and apply an input voltage equal to

the maximum and minimum full-scale common mode

expected.

2.

Use the following equation to determine the CMRR:

CMRR = 20 log

CM

OUT

V

V







where VCM is the common-mode voltage.

To minimize gain errors, follow these steps:

1.

Select gain = 10 with the control lines and apply a

differential input voltage.

2.

Adjust the 10 kΩ potentiometer to VOUT = 10 VIN

(adjust VIN magnitude as necessary).

3.

Repeat Step 1 and Step 2 for gain = 100 and gain = 1000,

adjusting the 1 kΩ and 100 Ω potentiometers, respectively.

The design shown in Figure 29 allows 0.1% gain accuracy and

100 dB common-mode rejection when ±1% resistors and ±10%

potentiometers are used.