Data Sheet

ADA4505-1/ADA4505-2/ADA4505-4

Rev. E | Page 15 of 24

Figure 55 displays a typical front-end section of an operational

amplifier with an on-chip charge pump.

Q2

Q1

VPP

VBIAS

+IN

–IN

OUT

CASCODE

STAGE

AND

RAIL-TO-RAIL

OUTPUT

STAGE

VDD

VSS

VPP = POSITIVE PUMPED VOLTAGE = VDD + 1.8V

Figure 55. Typical Front-End Section of an Op Amp

with Embedded Charge Pump

Figure 56 shows the typical response of two devices from Figure 12,

which shows the input offset voltage vs. input common-mode

voltage for 10 devices. Figure 56 is expanded to make it easier to

compare with Figure 54, which shows the typical input offset

voltage vs. common-mode voltage response in a dual differential

pair input stage op amp.

VCM (V)

0

–300

–100

100

300

1.5

3.5

5.0

1.0

0.5

2.5

4.5

4.0

3.0

2.0

–200

–150

–250

–50

0

50

150

200

250

VSY = 5V

TA = 25°C

Figure 56. Input Offset Voltage vs. Input Common-Mode Voltage Response

(Powered by a 5 V Supply; Results of Two Units Are Displayed)

This solution improves the CMRR performance tremendously.

For example, if the input varies from rail to rail on a 2.5 V

supply rail, using a part with a CMRR of 70 dB minimum,

an input-referred error of 790 μV is introduced. Another part

with a CMRR of 52 dB minimum generates a 6.3 mV error.

The ADA4505-x family CMRR of 90 dB minimum causes only

a 79 μV error. As with the PSRR error, there are complex ways

to minimize this error, but the ADA4505-x family solves this

problem without incurring unnecessary circuitry complexity or

increased cost.