4571 datasheet(39/126 Pages) RENESAS

39 / 126 page

Rev.1.02

May 25, 2007

Page 39 of 124

REJ03B0179-0102

4571 Group

RESET FUNCTION

System reset is performed by the followings:

• “L” level is applied to the RESET pin externally,

• System reset instruction (SRST) is executed,

• Reset occurs by watchdog timer,

• Reset occurs by built-in power-on reset

• Reset occurs by voltage drop detection circuit

Then when “H” level is applied to RESET pin, software starts

from address 0 in page 0.

(1) RESET pin input

System reset is performed certainly by applying “L” level to

RESET pin for 1 machine cycle or more when the following

condition is satisfied;

the value of supply voltage is the minimum value or more of the

recommended operating conditions.

Fig 40. Structure of reset pin and its peripherals

Fig 41. RESET pin input waveform and reset release timing

Power-on reset circuit

Watchdog reset signal

WEF

SRST instruction

Internal reset signal

(Note 1)

RESET pin

(Note 2)

Pull-up transistor

Voltage drop detection circuit

(Note 1)

Notes 1:

This symbol represents a parasitic diode.

2: Applied potential to RESET pin must be VDD or less.

0.3VDD

0.85VDD

(Note 1)

Program starts

(address 0 in page 0)

Reset input

1 machine cycle or more

RESET

f(RING)

Notes 1: Keep the value of supply voltage to the minimum value or more of the

recommended operating conditions.

2: It depends on the internal state at reset.

XIN input is counted 5400 to 5424 times (Note 2).

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