M62023L/P/FP

REJ03D0528-0200 Rev.2.00 Jun 15, 2007

Page 5 of 12

Configuration

<Power supply detector>

The internal reference voltage Vref is compared by means of a comparator with resistor divided voltage VR (resistor-

divided voltage produced by R1 and R2 from VIN).

If the input voltage is 3V, VR is set to 1.24V or higher, so the comparator output is at low level and the Ct output (Q1

collector output) is set to high level. If the input voltage drops to below 2.57V in an abnormal condition, VR becomes

below 1.24V, so the comparator output goes from low to high level and the Ct output, from high to low. The input

voltage at this point is called VSL. Next, when the input voltage, restored from abnormal state, has a rise, the

comparator output goes from high to low level and the Ct output, from low to high.

The comparator used for detection has 100mV hysteresis (

∆Vs), so that malfunctioning is prevented in case that the

input voltage slowly drops or VR nearly equals Vref.

2.0

3.0

1.0

0

2.4 2.5 2.6 2.7 2.8 2.9

<Delay Circuit>

Connecting an external capacitor to the Ct pin lets RES,

RES, CS, and VOUT be delayed due to RC transient

phenomenon (electric charge).

Delay time is determined as follows.

Delay time (tpd) = Ct×R3×In

3

Note: Ct is an external capacitance.

Taking into consideration the time taken by the oscillator of microcomputer to be stable, connect a 4.7

µF capacitor to

the Ct pin.

(As the response time of detection can be slowed due to internal structure depending on the rising rate of power supply,

avoid connecting a too large capacitance.)

INV1 (Vth)

Delayed output waveforms of Ct