Data Sheet

ADA4077-1/ADA4077-2/ADA4077-4

APPLICATIONS INFORMATION

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Rev. F | 23 of 25

analog components in the path, such as op amps, references, and

data converters. To help system designers predict the long-term

drift of circuits that use the ADA4077-1/ADA4077-2/ADA4077-4,

Analog Devices measured the offset voltage of multiple units

for 10,000 hours (more than 13 months) using a high precision

measurement system, including an ultrastable oil bath. To replicate

real-world system performance, the devices under test (DUTs) were

soldered onto an FR4 PCB using a standard reflow profile (as

defined in the JEDEC J-STD-020D standard), as opposed to testing

them in sockets. This manner of testing is important because

expansion and contraction of the PCB can apply stress to the

integrated circuit (IC) package and contribute to shifts in the offset

voltage.

The ADA4077-1/ADA4077-2/ADA4077-4 have extremely low long-

term drift (LTD). Figure 71 shows the LTD of the ADA4077-1 (SOIC

package). The red, blue, and green traces show sample units. Note

that the mean drift over 10,000 hours is less than 0.5 µV, or less

than 2% of their maximum specified offset voltage of 25 µV at room

temperature.

Figure 71. Measured Long-Term Drift of the ADA4077-1/ADA4077-2/

ADA4077-4 Offset Voltage over 10,000 Hours

TEMPERATURE HYSTERESIS

In addition to stability over time as described in the Long-Term Drift

section, it is useful to know the temperature hysteresis, that is,

the stability vs. cycling of temperature. Hysteresis is an important

parameter because it tells the system designer how closely the

signal returns to its starting amplitude after the ambient temperature

changes and subsequent return to room temperature. Figure 72

shows the change in input offset voltage as the temperature cycles

three times from room temperature to 125°C to −40°C and back

to room temperature. The dotted line is an initial preconditioning

cycle to eliminate the original temperature-induced offset shift from

exposure to production solder reflow temperatures. In the three full

cycles, the offset hysteresis is typically only 1 µV, or 1.5% of its

65 µV maximum offset voltage over the full operating temperature

range. The histogram in Figure 73 shows that the hysteresis is

larger when the device is cycled through only a half cycle, from

room temperature to 125°C and back to room temperature.

Figure 72. Change in Offset Voltage over Three Full Temperature Cycles

Figure 73. Histogram Showing the Temperature Hysteresis of the Offset

Voltage over Three Full Cycles and over Three Half Cycles