ADA4096-4ACPZ-R7 datasheet(20/25 Pages) AD

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ADA4096-2/ADA4096-4

Data Sheet

Rev. G | Page 20 of 25

THEORY OF OPERATION

INPUT STAGE

VCC

+IN

–IN

VEE

OVP

OUT

D10

Q20

Q19

D11

Q16

Q15

Q14

Q17

Q10

Q13

Q18

×1

Q12

Q11

Figure 53. Simplified Schematic, ADA4096-2

Figure 53 shows a simplified schematic of the ADA4096-2. The

input stage comprises two differential pairs (Q1 to Q4 and Q5

to Q8) operating in parallel. When the input common-mode

voltage approaches VCC − 1.5 V, Q1 to Q4 shut down as I1

reaches its minimum voltage compliance. Conversely, when the

input common-mode voltage approaches VEE + 1.5 V, Q5 to Q8

shut down as I2 reaches its minimum voltage compliance. This

topology allows for maximum input dynamic range because the

amplifier can function with its inputs at 200 mV outside the rail

(at room temperature).

As with any rail-to-rail input amplifier, VOS mismatch between

the two input pairs determines the CMRR of the amplifier. If

the input common-mode voltage range is kept within 1.5 V of

each rail, transitions between the input pairs are avoided, thus

improving the CMRR by approximately 10 dB (see Table 3 and

Table 4).

PHASE INVERSION

Some single-supply amplifiers exhibit phase inversion when

the input signal extends beyond the common-mode voltage

range of the amplifier. When the input devices become

saturated, the inverting and noninverting inputs exchange

functions, causing the output to move in the opposing

direction.

Although phase inversion persists for only as long as the inputs

are saturated, it can be detrimental to applications where the

amplifier is part of a closed-loop system. The ADA4096-2 family

is free from phase inversion over the entire common-mode

voltage range, as well as the overvoltage protected range that is

stated in the Absolute Maximum Ratings section, Table 5.

Figure 54 shows the ADA4096-2 in a unity-gain configuration

with the input signal at ±40 V and the amplifier supplies at

±10 V.

CH1 10.0V

CH2 10.0V

M2.00ms

A CH1

–3.6V

34.20%

Figure 54. No Phase Reversal

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