ADA4084-4ACPZ-R7 datasheet(32/36 Pages) AD

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ADA4084-1/ADA4084-2/ADA4084-4

Data Sheet

Rev. I | Page 32 of 36

LONG-TERM DRIFT

The stability of a precision signal path over its lifetime or

between calibration procedures is dependent on the long-term

stability of the analog components in the path, such as op amps,

references, and data converters. To help system designers

predict the long-term drift of circuits that use the ADA4084-1/

ADA4084-2/ADA4084-4, Analog Devices measured the offset

voltage of multiple units for 10,000 hours (more than 13 months)

using a high precision measurement system, including an

ultrastable oil bath. To replicate real-world system performance,

the devices under test (DUTs) were soldered onto an FR4 PCB

using a standard reflow profile (as defined in the JEDEC J-STD-

020D standard), as opposed to testing them in sockets. This

manner of testing is important because expansion and

contraction of the PCB can apply stress to the integrated circuit

(IC) package and contribute to shifts in the offset voltage.

The ADA4084-1/ADA4084-2/ADA4084-4 have extremely low

long-term drift, as shown in Figure 112. The red, blue, and

green traces show sample units. Note that the mean drift of the

ADA4084-1/ADA4084-2/ADA4084-4 over 10,000 hours is less

than 3 μV, or less than 3% of their maximum specified offset

voltage of 100 µV at room temperature.

–15

–5

–10

TIME (Hours)

VSY = 10V

27 UNITS

TA = 25°C

MEAN

MEAN PLUS ONE STANDARD DEVIATION

MEAN MINUS ONE STANDARD DEVIATION

SAMPLE 1

SAMPLE 2

SAMPLE 3

Figure 112. Measured Long-Term Drift of the ADA4084-1/ADA4084-2/

ADA4084-4 Offset Voltage over 10,000 Hours

TEMPERATURE HYSTERESIS

In addition to stability over time as described in the Long-Term

Drift section, it is useful to know the temperature hysteresis,

that is, the stability vs. cycling of temperature. Hysteresis is an

important parameter because it tells the system designer how

closely the signal returns to its starting amplitude after the

ambient temperature changes and subsequent return to room

temperature. Figure 113 shows the change in input offset

voltage as the temperature cycles three times from room

temperature to +125°C to −40°C and back to room temperature.

The dotted line is an initial preconditioning cycle to eliminate

the original temperature-induced offset shift from exposure to

production solder reflow temperatures. In the three full cycles,

the offset hysteresis is typically only 4 μV, or 2% of its 200 µV

maximum offset voltage over the full operating temperature

range. The histogram in Figure 114 shows that the hysteresis is

larger when the device is cycled through only a half cycle, from

room temperature to 125°C and back to room temperature.

TEMPERATURE (°C)

VSY = 10V

100

–100

–80

–40

–20

100

120

–20

–40

–60

PRECONDITION

CYCLE 1

CYCLE 2

CYCLE 3

Figure 113. Change in Offset Voltage over Three Full Temperature Cycles

OFFSET VOLTAGE HYSTERESIS (µV)

–40

–32

–24

–18

–8

HALF CYCLE

FULL CYCLE

VSY = 10V

27 UNITS × 3 CYCLES

HALF CYCLE = +26°C, +125°C, +26°C

FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C

Figure 114. Histogram Showing the Temperature Hysteresis of the Offset

Voltage over Three Full Cycles and over Three Half Cycles

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