M58LT128HSB datasheet(13/110 Pages) STMICROELECTRONICS

13 / 110 page

M58LT128HST, M58LT128HSB

Signal descriptions

13/110

2.7

Latch Enable (L)

Latch Enable latches the address bits on its rising edge. The address latch is transparent

when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.

2.8

Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read

operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous

read and in write operations.

2.9

Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the

output bus are valid. This output is high impedance when Chip Enable is at VIH, Output

Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or

one clock cycle in advance.

2.10

VDD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (Read, Program and Erase).

2.11

VDDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered

independently from VDD.

2.12

VPP program supply voltage

VPP is both a control input and a power supply pin. The two functions are selected by the

voltage range applied to the pin.

If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case

a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in

the VPP1 range enables these functions (see Tables 20 and 21, DC Characteristics for the

relevant values). VPP is only sampled at the beginning of a program or erase; a change in its

value after the operation has started does not have any effect and program or erase

operations continue.

If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be

stable until the Program/Erase algorithm is completed.

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