M41ST85WMH6F datasheet(13/34 Pages) STMICROELECTRONICS

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M41ST85W

CLOCK OPERATION

The

eight

byte

clock

(see

Table

2., page 14) is used to both set the clock and to

read the date and time from the clock, in a binary

coded decimal format. Tenths/Hundredths of Sec-

onds, Seconds, Minutes, and Hours are contained

within the first four registers.

Note: A WRITE to any clock register will result in

the Tenths/Hundredths of Seconds being reset to

“00,” and Tenths/Hundredths of Seconds cannot

be written to any value other than “00.”

Bits D6 and D7 of Clock Register 03h (Century/

Hours Register) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or from '1' to '0' at the turn of the century (de-

pending upon its initial state). If CEB is set to a '0,'

CB will not toggle. Bits D0 through D2 of Register

04h contain the Day (day of week). Registers 05h,

06h, and 07h contain the Date (day of month),

Month and Years. The ninth clock register is the

Control Register (this is described in the Clock

Calibration section). Bit D7 of Register 01h con-

tains the STOP Bit (ST). Setting this bit to a '1' will

cause the oscillator to stop. If the device is expect-

ed to spend a significant amount of time on the

shelf, the oscillator may be stopped to reduce cur-

rent drain. When reset to a '0' the oscillator restarts

within one second.

The eight Clock Registers may be read one byte at

a time, or in a sequential block. The Control Reg-

ister (Address location 08h) may be accessed in-

dependently. Provision has been made to assure

that a clock update does not occur while any of the

eight clock addresses are being read. If a clock ad-

dress is being read, an update of the clock regis-

ters will be halted. This will prevent a transition of

data during the READ.

Power-down Time-Stamp

When a power failure occurs, the Halt Update Bit

(HT) will automatically be set to a '1.' This will pre-

vent the clock from updating the TIMEKEEPER®

registers, and will allow the user to read the exact

time of the power-down event. Resetting the HT

Bit to a '0' will allow the clock to update the TIME-

KEEPER registers with the current time. For more

information, see Application Note AN1572.

TIMEKEEPER® Registers

The M41ST85W offers 20 internal registers which

contain Clock, Alarm, Watchdog, Flag, Square

Wave and Control data. These registers are mem-

ory locations which contain external (user accessi-

ble) and internal copies of the data (usually

referred to as BiPORT™ TIMEKEEPER cells). The

external copies are independent of internal func-

tions except that they are updated periodically by

the simultaneous transfer of the incremented inter-

nal copy. The internal divider (or clock) chain will

be reset upon the completion of a WRITE to any

clock address.

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). The update will resume ei-

ther due to a Stop Condition or when the pointer

increments to a non-clock or RAM address.

TIMEKEEPER and Alarm Registers store data in

BCD. Control, Watchdog and Square Wave Reg-

isters store data in Binary Format.

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