| 数据搜索系统,热门电子元器件搜索 |
|
ADA4062-2BRZ-R7 数据表(PDF) 12 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADA4062-2BRZ-R7 数据表(HTML) 12 Page - Analog Devices |
|
12 / 20 page ![]() ADA4062-2/ADA4062-4 Rev. B | Page 12 of 20 –2 0 2 4 2 0 –2 INPUT OUTPUT TIME (2µs/DIV) VSY = ±5V AV =–10 Figure 41. Positive Overload Recovery TIME (2µs/DIV) +20mV –20mV 0V INPUT OUTPUT ERROR BAND VSY = ±5V CL = 100pF RL = 10kΩ Figure 42. Positive Settling Time to 0.1% TIME (2µs/DIV) +20mV –20mV 0V INPUT OUTPUT ERROR BAND VSY = ±5V CL = 100pF RL = 10kΩ Figure 43. Negative Settling Time to 0.1% –5 0 5 10 15 –2 0 2 INPUT OUTPUT TIME (2µs/DIV) VSY = ±15V AV =–10 Figure 44. Positive Overload Recovery TIME (2µs/DIV) +100mV –100mV 0V INPUT OUTPUT ERROR BAND VSY = ±15V CL = 100pF RL = 10kΩ Figure 45. Positive Settling Time to 0.1% TIME (2µs/DIV) +100mV –100mV 0V INPUT OUTPUT ERROR BAND VSY = ±15V CL = 100pF RL = 10kΩ Figure 46. Negative Settling Time to 0.1% |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |