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PT0239L (06/07)

Ver: 0

5

Data Sheet

PT7C4050

PLL with Integrated VCXO

Function Description

LOS detection

LOS-OUT1 provides output alarm flag when REF-CLK1 is lost. The LOS output is set to logic high after 256 consecutive

FB-CLK (CLKIN) periods with no REF-CLK1 (DATAIN) transitions. As soon as a transition occurs at REF-CLK1 (DATAIN),

LOS is reset to a logic low.

Divider output signals

The internal divider N is 2,4,8, ------, 8192, and creates 5 kinds of 8KHZ frame signals: F0N, F8, F16N, RSP, TSP. F0N

outputs to CLK-OUT3 pin, F16N outputs to CLK-OUT4 pin. The F8, TSP, RSP can be selected by S4:1 (bond option) and output

to CLK-OUT2 pin.

8KHZ frame signals’ generator based on 32MHZ VCXO frequency. All signals are compatible with 4409 DPLL product.