PIC16F010-ESLASHMCSQTP datasheet(17/116 Pages) MICROCHIP

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Preliminary

DS41268C-page 15

PIC12F510/16F506

4.0

MEMORY ORGANIZATION

The PIC12F510/16F506 memories are organized into

program memory and data memory. For devices with

more than 512 bytes of program memory, a paging

scheme is used. Program memory pages are accessed

using STATUS register bit PA0. For the PIC12F510 and

PIC16F506, with data memory register files of more

than 32 registers, a banking scheme is used. Data

memory banks are accessed using the File Select

4.1

Program Memory Organization for

the PIC12F510/16F506

The

PIC12F510/16F506

devices

have

10-bit

Program Counter (PC) capable of addressing a 2K x 12

program memory space.

Only the first 1K x 12 (0000h-03FFh) are physically

implemented (see Figure 4-1). Accessing a location

above these boundaries will cause a wraparound

within the 1K x 12 space. The effective Reset vector

is a 0000h (see Figure 4-1). Location 03FFh contains

the internal clock oscillator calibration value. This

value should never be overwritten.

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12F510/16F506

CALL

, RETLW

PC<11:0>

Stack Level 1

Stack Level 2

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector(1)

Note

Address 0000h becomes the effective

Reset vector. Location 03FFh contains

the MOVLW XX internal oscillator

calibration value.

512 Word

1024 Word

03FFh

0400h

On-chip Program

Memory

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