AD8613/AD8617/AD8619

Data Sheet

Rev. H | Page 14 of 16

Figure 41. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

Figure 42. 5-Lead Thin Small Outline Transistor Package [TSOT-23]

(UJ-5)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-203-AA

1.00

0.90

0.70

0.46

0.36

0.26

2.20

2.00

1.80

2.40

2.10

1.80

1.35

1.25

1.15

0.10 MAX

1.10

0.80

0.40

0.10

0.22

0.08

3

12

4

5

0.65 BSC

COPLANARITY

0.10

SEATING

PLANE

0.30

0.15

*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

1.60 BSC

2.80 BSC

1.90

BSC

0.95 BSC

0.20

0.08

0.60

0.45

0.30

8°

4°

0°

0.50

0.30

0.10 MAX

*1.00 MAX

*0.90 MAX

0.70 MIN

2.90 BSC

54

12

3

SEATING

PLANE