Output

&

Input

Rs

V

CC

CC(min)

S(max)

IH

V

2.4 V

R

n I

CCP

S(min)

V

5.5 V

R

1 mA

13

SN5400, SN54LS00, SN54S00

SN7400, SN74LS00, SN74S00

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SDLS025D – DECEMBER 1983 – REVISED MAY 2017

Product Folder Links: SN5400 SN54LS00 SN54S00 SN7400 SN74LS00 SN74S00

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Copyright © 1983–2017, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

When using multiple bit logic, devices inputs must never float.

Devices with multiple-emitter inputs (SN74 and SN74S series) need special care. Because no voltage greater

than 5.5 V must be applied to the inputs (if exceeded, the base-emitter junction at the inputs breaks down), the

inputs of these devices must be connected to the supply voltage, VCC, through series resistor, RS (see Figure 5).

This resistor must be dimensioned such that the current flowing into the gate or gates, which results from

overvoltage, does not exceed 1 mA. However, because the high-level input current of the circuits connected to

the gate flows through this resistor, the resistor must be dimensioned so that the voltage drop across it still

allows the required high level. Equation 1 and Equation 2 are for dimensioning resistor, RS, and several inputs

can be connected to a high level through a single resistor if the following conditions are met.

(1)

where

•

n = number of inputs connected

•

IIH = high input current (typical 40 µA)

•

VCC(min) = minimum supply voltage, VCC

•

VCCP = maximum peak voltage of the supply voltage, VCC (about 7 V)

(2)

11.2 Layout Example

Figure 5. Series Resistor Connected to Unused Inputs of Multiple-Emitter Transistors