Data Sheet

ADL8122

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 28

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RBIAS

Bias Setting Resistor. Connect a resistor between RBIAS and VDDx to set IDQ. See Figure 94 and Table 9 for more details.

See Figure 4 for the interface schematic.

2

VBIAS

Bias Setting Voltage Output. VBIAS sets the bias voltage for the RFIN pin. Connect VBIAS to RFIN using an inductor or

ferrite bead as shown in Figure 94. See Figure 5 for the interface schematic.

3, 6

GND

Ground. Connect to a ground plane that has low electrical and thermal impedance. See Figure 6 for the interface

schematic.

4

RFIN

RF Input. The RFIN pin is DC-coupled and matched to 50 Ω. See Figure 7 for the interface schematic.

5

RFOUT/VDD1

RF Output and Drain Bias Voltage. The RF output is DC-coupled and also serves as the drain biasing node. For the drain

bias voltage, connect a DC bias network to provide the drain current and AC-couple the RF output path. See Figure 8 for

the interface schematic.

7

NIC

No Internal Connection. The NIC pin is not connected internally. For normal operation, connect this pin to ground.

8

VDD2

Drain Bias. Connect the VDD2 pin to a common supply with VDD1. See Figure 9 for the interface schematic.

GROUND PADDLE

Ground Paddle. Connect the ground paddle to a ground plane that has low electrical and thermal impedance.

INTERFACE SCHEMATICS

Figure 4. RBIAS Interface Schematic

Figure 5. VBIAS Interface Schematic

Figure 6. GND Interface Schematic

Figure 7. RFIN Interface Schematic

Figure 8. RFOUT/VDD1 Interface Schematic

Figure 9. VDD2 Interface Schematic