STW5094ADTLF datasheet(20/51 Pages) STMICROELECTRONICS

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STw5094A

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Control Register CR15 Functions (Address: 0x0F)

* state at power on initialization

Control Register CR16 Functions (Address: 0x10)

(1) significant in 18

⁄ 20 ⁄ 24 bit per word mode only

(2) Left Channel data is always received first.

(3) First bit delay, in 18

⁄ 20 ⁄ 24 bit per word mode, is applied only if word is left justified.

*: state at power on initialization

7654

3210

Function

BZ(5:0)

Buzzer output disabled (set to 0)

Buzzer output enabled

Duty Cycle is intended as the relative width of logic 1

Duty cycle is intended as the relative width of logic 0

msb

lsb

Binary equivalent of the decimal number used to calculate the

duty cycle, using the formula:

Duty Cycle = BZ(5:0) x 0.78125%

7654

3210

Function

POL

ORD

DIF

INV

FOR

SCL

PREC(1:0)

AMCK Not Inverted

AMCK Inverted

Audio I/F data order, the MSB is received first (I2S)

Audio I/F data order, the LSB is received first

Audio I/F data alignment, the word is left justified (I2S)(1) *

Audio I/F data alignment, the word is right justified

(1)

LRCK polarity, when LRCK=0 Left data is received

(I2S) (2) *

LRCK polarity, when LRCK=1 Left data is received

(2)

Audio I/F format, I2S format (first bit is delayed)

(3) *

Audio I/F format, non delayed formats

SCK polarity, SDI and LRCK sampled on the rising edge

(I2S)

SCK polarity, SDI and LRCK sampled on the falling edge

Audio I/F data width 16 bit (32 SCK clocks per frame)

Audio I/F data width 18 bit (64 SCK clocks per frame)

Audio I/F data width 20 bit (64 SCK clocks per frame)

Audio I/F data width 24 bit (64 SCK clocks per frame)

STW5094ADTLF 数据表(PDF) 20 Page - STMicroelectronics

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