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PACE1757M 数据表(PDF) 29 Page - Pyramid Semiconductor Corporation |
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PACE1757M 数据表(HTML) 29 Page - Pyramid Semiconductor Corporation |
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29 / 34 page  PACE 1757 M/ME Page 29 of 34 Document # MICRO-10 REV B COMBO REGISTER MAP DEFINITIONS CONTROL REGISTER (1F50/9F50) (Default = 00C6H) QR1 Enable error detection/correction or parity checking/generation for memory addresses 00000H-3FFFFH. QR2 Enable error detection/correction or parity checking/generation for memory addresses 40000H-7FFFFH QR3 Enable error detection/correction or parity checking/generation for memory addresses 80000H-BFFFFH. QR4 Enable error detection/correction or parity checking/generation for memory addresses C0000H-FFFFFH. ODD Enable odd parity, 1 = ODD, 0 = EVEN EEI Enable error detection/correction (EDAC) on instruction fetch only. EED Enable error detection/correction (EDAC) on operand (data) fetch only. EPR Enable parity detection function. (If both EPR and either EEI or EED are enabled, EEI or EED will take preference.) SPD Enable 1 wait state on MMU cache miss cycle (1 = 1 WAIT, 0 = NO WAIT). WPT Enable protected write strobe (WR PROT PIN). 1: WR PROT = write protected strobe 0: WR PROT = write protect level (1 = write protect memory) EB1 Enable block 1 of unimplemented memory (as defined in unimplemented memory register 1). EB2 Enable block 2 of unimplementd memory (as defined in unimplemented memory register 2). EIO Enable illegal PIO detection (as defined in last implemented input and output registers, and MIL-STD-1750A reserved I/O space). GPT Enable global memory protect (Set by RESET, and reset by I/O command 4003). DMX Demultiplexed Address/data Bus in DMA cycles. DLP Logical/Physical DMA (1 = LOGICAL, 0 = Physical). CONTROL REGISTER 1 (1F51) (Default = C3FFH) WA0/ Number of WAIT STATES on RDYA WA1 SPI Enable illegal PIO detection for MIL- STD1750A spare I/O spaces. PEG Determines what is generated when both EDAC and parity checks are disabled. IDL Enables/disables the genertion of an idle cycle betwee BUS REQ and BUS GNT, during read cycles, allowing for one additional clock cycle to release the IB. UNIMPLEMENTED MEMORY REGISTER 1 (1F55) BL1 LO Low boundary of unimplemented block 1 of memory. BL1 HI High boundary of unimplemente block 1 of memory. UNIMPLEMENTED MEMORY REGISTER 2 (1F56) BL2 LO Low boundary of unimplemented block 2 of memory. BL2 HI High boundary of unimplemented block 2 of memory. FIRST UNIMPLMENTED OUTPUT COMMAND REGISTER (1F57) BITS 0:5 Not used. BITS 6:15 First unused sequential PIO output command. FIRST UNIMPLMENTED INPUT COMMAND REGISTER (1F58) BITS 0:5 Not used. BITS 0:6 First unused sequential PIO input command. FIRST FAILING ADDRESS REGISTER (1F59) PADR (4:19) 16 LSB of the physical address of the first failure. FIRST FAILING DATA REGISTER (1F5B) BITS 0:15 "1" indicates the position of the wrong/ corrected bit in the data word. MEMORY FAULT STATUS REGISTER (A00D) LPA Page address within the group. ID Instruction/data AS Group address. |
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