16

DS613F1

CS4344/5/6/8

When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN

for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always

be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the

DAC output automatically goes to it’s zero data state.

Figure 12. CS4344/5/6/8 Initialization and Power-down Sequence

USER: Apply Power

Wait State

USER: Apply LRCK

M CLK/LRCK Ratio Detection

USER: Applied SCLK

USER: Rem ove

LRCK

USER: change

MCLK/LRC K ratio

SCLK m ode = internal

SCLK m ode = external

Norm al O peration

De-em phasis

available

Analog Output

is G enerated

Norm al Operation

De-em phasis

not available

Analog Output

is Generated

USER: change

MCLK/LRCK ratio

USER: Rem ove

MCLK

USER: Rem ove

LRCK

USER: Rem ove

MCLK

USER: Apply M CLK

Power-Down State

VQ and outputs low

VQ and outputs

ram p down

VQ and outputs

ram p down

VQ and outputs ram p up

USER: No SCLK