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CS5342 数据表(PDF) 13 Page - Cirrus Logic |
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CS5342 数据表(HTML) 13 Page - Cirrus Logic |
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13 / 21 page ![]() DS608F1 13 CS5342 3. TYPICAL CONNECTION DIAGRAM Figure 17. Typical Connection Diagram FILT+ V 0.1 µF A/D CONVERTER SCLK CS5342 MCLK VQ 1 µF + RST VA L 1 µF 2.5V to 5V 1 µF + + SDOUT GND LRCK Power Down and Mode Settings Audio Data Processor Timing Logic and Clock 0.1 µF 0.1 µF 0.1 µF REFGND 1 µF + AINL AI NR 3.3V to 5V 1 µF + 0.1 µF 3.3V to 5V Ω 5.1 VD 0.1 µF Ω 10 k VL or GND Pull-up to VL for I 2S Pull-down to GND for LJ M0 M1 Analog Input Buffer Figure 15 Resistor may only be used if VD is derived from VA. If used, do not drive any other logic from VD Capacitor value affects low frequency distortion performance as described in Section 4.8 1 2 3 See Note 2 on page 4 4 4 4 1 2 3 |
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