CS42448 datasheet(21/64 Pages) CIRRUS

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DS648F2

CS42448

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE

(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL =30pF)

Notes:

21. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

22. Guaranteed by design.

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

100

kHz

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

µs

Clock Low time

tlow

4.7

µs

Clock High Time

thigh

4.0

µs

Setup Time for Repeated Start Condition

tsust

4.7

µs

SDA Hold Time from SCL Falling

(Note 21)

thdd

µs

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

(Note 22)

trc

-1

µs

Fall Time SCL and SDA

(Note 22)

tfc

-300

Setup Time for Stop Condition

tsusp

4.7

µs

Acknowledge Delay from SCL Falling

tack

300

1000

t buf

t hdst

lo w

hdd

t high

t sud

Stop

Start

SDA

SCL

t irs

RS T

hdst

t rc

t fc

t sust

t susp

Sta rt

Stop

R e pe ate d

t rd

t fd

t ack

Figure 8. Control Port Timing - I²C Format

CS42448 数据表(PDF) 21 Page - Cirrus Logic

CS42448 数据表(HTML) 21 Page - Cirrus Logic

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