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PXAS30 数据表(PDF) 35 Page - NXP Semiconductors |
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PXAS30 数据表(HTML) 35 Page - NXP Semiconductors |
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35 / 52 page ![]() Philips Semiconductors Preliminary specification XA-S3 XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V), I2C, 2 UARTs, 16 MB address range 2000 Dec 01 35 8-BIT MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70°C for commercial, Tamb = –40 to +85°C for industrial, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT AVDD Analog supply voltage 2.7 3.3 V AIDD Analog supply current (operating) Port 5 = 0 to AVDD 2.5 mA AIID Analog supply current (Idle mode) 2.5 µA AIPD Analog supply current (Power-Down mode) Commercial temperature range 100 µA Industrial temperature range 150 µA AVIN Analog input voltage AVSS –0.2 AVDD +0.2 V RREF Resistance between VREF+ and VREF– 125 225 k Ω CIA Analog input capacitance 15 pF DLe Differential non-linearity1, 2, 3 ±1 LSB ILe Integral non-linearity1, 4 ±1 LSB OSe Offset error1, 5 ±2.5 LSB Ge Gain error1, 6 ±1 % Ae Absolute voltage error1, 7 ±3 LSB MCTC Channel-to-channel matching ±1 LSB Ct Crosstalk between inputs of port8 0 – 100 kHz –60 dB NOTES: 1. Conditions: AVREF– = 0 V; AVREF+ = 3.07 V. 2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25. 3. The ADC is monotonic, there are no missing codes. 4. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25. 5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. See Figure 25. 6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25. 7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design. |
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