ICS9212-13 datasheet(2/7 Pages) ICST

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ICS9212-13

0272F—08/08/07

Pin Descriptions

Pin #

Name

Type

Description

VDDREF

REFV

Reference voltage for refclk, to be connected to CK133

REFCLK

Reference clock, to be connected to CK133

VDD1

PWR

3.3 V power supply used for PLL

GND1

PWR

Ground for PLL

GND3

PWR

Ground for control inputs

6,7

PCLK/M, SYNCLK/N

Phase controller input, used to drive a phase aligner

that adjusts the phase of the busclk.

GND2

PWR

Ground for phase aligner

VDD2

PWR

3.3 V power supply used for phase aligner

VDDPD

REFV

Reference voltage for phase detector inputs connected

to the controller

BUSCLK_ STOP#

Active low output enable/disable

PD#

3.3V CMOS active low power down, the device is

powered down when the "(PD#) =0"

14,15

MULTI (0:1)

3.3V CMOS PLL Multiplier select, logic for selecting

the multiply ratio for the PLL from the input REFCLK

VDD_OUT

PWR

3.3V supply for clock out puts

GND_OUT

PWR

Ground for clock outputs

BUSCLKC

OUT

Out put clock connected to the Rambus channel. This

output is the complement of BUSCLK

N/C

NOT USED

BUSCLKT

OUT

Output clock connected to the Rambus channel. This

output is the true component of BUSCLK

GND_OUT

PWR

Ground for clock outputs

VDD_OUT

PWR

3.3V supply for clock out puts

13,23,24

FS(0:2)

3.3V CMOS Mode control, used in selecting bypass,

test, normal, and output test (OE)

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