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F/S-Mode Protocol

HS-Mode Protocol

Start

Condition

SDA

Stop

Condition

SDA

SCL

S

P

SCL

DAC5571

SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005

THEORY OF OPERATION (continued)

Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data

transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in

this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as

HS-mode. The DAC5571 supports 7-bit addressing; 10-bit addressing and general call address are not

supported.

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The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

recognize a start condition.

•

The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave

device with a matching address generates an acknowledge (see Figure 43) by pulling the SDA line low

during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a

communication link with a slave has been established.

•

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from

the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So

an acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long

as necessary.

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To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low

to high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link

stop condition, all devices know that the bus is released, and they wait for a start condition followed by a

matching address.

•

When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.

•

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the

HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps

operation.

•

The master then generates a repeated start condition (a repeated start condition has the same timing as the

start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that

transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the

internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated

start conditions should be used to secure the bus in HS-mode.

Figure 41. START and STOP Conditions

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