LP3950 datasheet(11/31 Pages) NSC

11 / 31 page

2C Compatible Interface (Continued)

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with

the most significant bit (MSB) being transferred first. Each

byte of data has to be followed by an acknowledge bit. The

acknowledge related clock pulse is generated by the master.

The transmitter releases the SDA line (HIGH) during the

acknowledge clock pulse. The receiver must pull down the

SDA line during the 9th clock pulse, signifying an acknowl-

edge. A receiver which has been addressed must generate

an acknowledge after each byte has been received.

After the START condition, the I

2C master sends a chip

address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LP3950

address is 50’h or 51’h. The selection of the address is done

by connecting SI pin to V

DDIO (51 hex) or GND (50 hex). For

the eighth bit, a “0” indicates a WRITE and a “1” indicates a

READ. The second byte selects the register to which the

data will be written. The third byte contains data to write to

the selected register.

When a READ function is to be accomplished, a WRITE

function must precede the READ function, as shown in

Figure 9 .

20129311

FIGURE 6. Start and Stop Conditions

20129312

FIGURE 7. I

2C Chip Address

20129313

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = chip address, 50’h or 51’h for LP3950.

FIGURE 8. I

2C Write Cycle

LP3950 数据表(PDF) 11 Page - National Semiconductor (TI)

LP3950 数据表(HTML) 11 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

数据表下载