P4C1048L

Page 5 of 12

Document # SRAM129 REV D

Notes:

1.

WE is HIGH for READ cycle.

2.

CE and OE are LOW for READ cycle.

3. ADDRESS must be valid prior to, or coincident with later of

CE transition LOW.

READ CYCLE NO. 2 (ADDRESS CONTROLLED)

READ CYCLE NO. 3 (

CE

CE

CE

CE

CE CONTROLLED)

4. Transition is measured ± 200 mV from steady state voltage prior to change,

with loading as specified in Figure 1. This parameter is sampled and not

100% tested.

5. READ Cycle Time is measured from the last valid address to the first

transitioning address.