IDT7130SA/LA and IDT7140SA/LA

High-Speed 1K x 8 Dual-Port Static SRAM

Military, Industrial and Commercial Temperature Ranges

16

Truth Tables

Truth Table III — Address BUSY

Arbitration

NOTES:

1. Pins

IDT7140 (slave).

outputs. On slaves the

2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs

of this port. 'H' if the inputs to the opposite port became stable after the address and

result.

3. Writes to the left port are internally ignored when

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when

the pin.

NOTES:

2. If

BUSY = L, data is not written.

3. If

NOTES:

1. Assumes

2. If

3. If

4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE

Function

R/

W

CE

OE

X

H

X

Z

XH

X

Z

LL

X

HL

L

Data in Memory Output on Port

(3)

H

L

H

Z

High Impedance Outputs

2689 tbl 13

Left Port

Right Port

Function

R/

R/

L

L

X3FF

XXXX

X

Set Right

XX

X

X

X

X

L

L

3FF

Reset Right

XX

X

X

L

L

X

3FE

X

Set Left

XL

L

3FE

X

X

XXX

Reset Left

2689 tbl 14

Inputs

Outputs

Function

X

X

NO MATCH

H

H

Normal

H

X

MATCH

H

H

Normal

X

H

MATCH

H

H

Normal

L

L

MATCH

(2)

(2)

Write Inhibit

(3)

2689 tbl 15