CY29940AI datasheet(1/7 Pages) CYPRESS

部件名	CY29940AI

功能描述	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

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制造商	CYPRESS [Cypress Semiconductor]

网页	http://www.cypress.com

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2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

CY29940

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document #: 38-07283 Rev. *C

Revised April 4, 2006

Features

• 200-MHz clock support

• LVPECL or LVCMOS/LVTTL clock input

• LVCMOS/LVTTL compatible inputs

• 18 clock outputs: drive up to 36 clock lines

• 60 ps typical output-to-output skew

• Dual or single supply operation:

— 3.3V core and 3.3V outputs

— 3.3V core and 2.5V outputs

— 2.5V core and 2.5V outputs

• Pin compatible with MPC940L, MPC9109

• Available in Commercial and Industrial temperature

• 32-pin LQFP package

Description

The CY29940 is a low-voltage 200-MHz clock distribution buff-

er with the capability to select either a differential LVPECL or

a LVCMOS/LVTTL compatible input clock. The two clock

sources can be used to provide for a test clock as well as the

primary system clock. All other control inputs are LVC-

MOS/LVTTL compatible. The eighteen outputs are 2.5V or

3.3V LVCMOS/LVTTL compatible and can drive 50

Ω series or

parallel terminated transmission lines. For series terminated

transmission lines, each output can drive one or two traces

giving the device an effective fanout of 1:36. Low out-

put-to-output skews make the CY29940 an ideal clock distri-

bution buffer for nested clock trees in the most demanding of

synchronous systems.

Note:

1.

PD = Internal Pull-Down, PU = Internal Pull-up

Block Diagram

Pin Configuration

PECL_CLK

PECL_CLK#

0

1

TCLK

TCLK_SEL

VDDC

18

Q0-Q17

VDD

CY29940

Q6

Q7

Q8

VDD

Q9

Q10

Q11

VSS

TCLK

TCLK_SEL

PECL_CLK

PECL_CLK#

VDD

VDDC

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

Pin Description[1]

Name

PWR

I/O

Description

5

PECL_CLK

I, PU

PECL Input Clock

6

PECL_CLK#

I, PD

PECL Input Clock

3

TCLK

I, PD

External Reference/Test Clock Input

9, 10, 11, 13, 14,

15, 18, 19, 20, 22,

23, 24, 26, 27, 28,

30, 31, 32

Q(17:0)

VDDC

O

Clock Outputs

4

TCLK_SEL

I, PD

Clock Select Input. When LOW, PECL clock is selected and when HIGH

TCLK is selected.

8, 16, 29

VDDC

3.3V or 2.5V Power Supply for Output Clock Buffers

7, 21

VDD

3.3V or 2.5V Power Supply

1, 2, 12, 17, 25

VSS

Common Ground

[+] Feedback

类似零件编号 - CY29940AI

制造商	部件名	数据表	功能描述
Cypress Semiconductor	CY29940AI	189Kb / 7P	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
	CY29940AI-1	200Kb / 7P	2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer
	CY29940AI-1T	200Kb / 7P	2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer
	CY29940AIT	189Kb / 7P	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

More results

类似说明 - CY29940AI

制造商	部件名	数据表	功能描述
Cypress Semiconductor	CY29940	189Kb / 7P	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
	CY29947	103Kb / 7P	2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer
	CY29946	111Kb / 6P	2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer
	CY29942	184Kb / 7P	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
	CY29948	108Kb / 7P	2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
	B9940L	182Kb / 5P	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
	CY29943	188Kb / 7P	2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer
	CY29948	191Kb / 8P	2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
	CY29940-1	200Kb / 7P	2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer
	CY29949	328Kb / 7P	2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer

More results

CY29940AI 数据表(PDF) 1 Page - Cypress Semiconductor

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类似零件编号 - CY29940AI

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CY29940AI 数据表(PDF) 1 Page - Cypress Semiconductor

CY29940AI 数据表(HTML) 1 Page - Cypress Semiconductor

类似零件编号 - CY29940AI

类似说明 - CY29940AI

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