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ST10F269ZX 数据表(PDF) 147 Page - STMicroelectronics |
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ST10F269ZX 数据表(HTML) 147 Page - STMicroelectronics |
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147 / 184 page  ST10F269 147/184 between two consecutive edges of the CPU clock, called “TCL”. The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F269. The example for PLL operation shown in Figure 68 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 68 : Generation Mechanisms for the CPU Clock TCL TCL TCL TCL fCPU fXTAL fCPU fXTAL Phase locked loop operation Direct Clock Drive TCL TCL fCPU fXTAL Prescaler Operation |
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